1. Technical Field
The embodiments described herein generally relates to debugging systems and processes and in particular to debugging of devices that can operate in different power modes. More particularly, the embodiments presented herein relate to debugging of devices when the device exits a low power mode.
2. Description of the Related Art
Most electronic devices are designed to enter into a low power mode under one or more conditions. These entries into a low power mode can be triggered by the device's processing core(s), which cause the device's power management module (PMM) to remove and/or reduce power allocated to the processing cores and to other functional components and/or sub-devices. When power is removed from most of these devices, all states maintained by those devices before the power is removed can be lost. When the device is later powered back on or exits from the low power state, the processing cores and other components resume operation without the benefit of the states that existed prior to entry into the low power mode.
During standard debugging operations on these devices (which are externally connected to the machine on which the debug process executes), entry by the device into the low power state can cause a resulting failure (crash) in the debug session. Alternatively, when the debugger is robust enough to pause its debug process (i.e., not crash due to the communication disconnect/failure with the device) and resume debug operations on the device when debugger detects that the device has returned from the low power state, important debug information is lost during the delay time from which the processor cores resume execution on the device and the debugger receives a signal indicating the device has returned from the low power mode. Further, there is no mechanism that enables the debugger to account for and/or debug the device's entry into and subsequent exit from the low power mode.